1. Field of the Invention
The present invention relates generally to the field of semiconductor technology. More particularly, the present invention relates to a method for fabricating a trench type transistor.
2. Description of the Prior Art
As known in the art, the rise of on-resistance of traditional planar power DMOS devices (DMOS) is contributed from the channel region, the accumulation layer and junction field effect transistor (JFET).
In order to reduce the resistance of the above-mentioned area, trench type power devices (UMOS) are proposed. Since JFET region does not exist in a UMOS, the cell size can be reduced and the channel density is increased, thereby resulting in a lower on-resistance. However, as the cell size shrinks, the gap or space between the gate and the contact window also reduces, leading to overly issues.